1. Technical Field of the Invention
The invention relates generally to the communication devices; and, more particularly, it relates to the field of amplification and equalization that may be implemented within such communication devices.
2. Description of Related Art
High speed circuit techniques such as current-controlled CMOS (or C3MOS) logic have been developed that have brought about marked increase in the speed of circuitry fabricated using standard CMOS process technology.
To enable a communication system to adapt to various input data communication channel types, it is highly desirable for a wideband data amplifier to be able to provide both a flat frequency response as well to provide high-pass responses with different levels of boost. In another implementation (U.S. Patent Application Publication Number: 20040028158), two separate data paths are provided for the input data: (1) one having a flat frequency response and (2) the other having a high-pass frequency response. The signals, after having passed through the two different paths, are then combined together at a summing stage. The relative strength of the two paths can be adjusted and thus enable the overall data path to have a high-pass response with different level of boost and high frequency. When the high-pass path is completely turned off, a flat frequency response can be obtained.
FIG. 1 illustrates a prior art two path embodiment 100 of an adjustable amplifier/equalizer. For transmission rates of 10 Gbps (Giga-bits per second) or higher, the data amplifier or equalizer generally consume a significant amount of power. In the two-path approach for adjustable equalization, three high-speed blocks needs to be powered up (i.e., a flat gain stage 110, a high-pass gain stage 120, and control 130 that is operable to control each of the flat gain stage 110 and the high-pass gain stage 120). If the summer is included in this consideration, then three high-speed blocks are employed. The summer is especially power hungry because it has two pairs of full-rate data input. This adds a significant amount of parasitic loading to the high speed data path.
Further more, the input data are connected to both the flat gain stage 100 and the high-pass gain filter stage 120. If this combined input signal (i.e., which is provided to both the flat gain stage 100 and the high-pass gain filter stage 120) is connected to the output of a front buffer, then this configuration significantly increases the loading to the previous stage. This has the undesirable effect and deleterious effect of reducing the bandwidth of the data path. Moreover, if the combined input is connected to the input pads of the receiver directly, it will cause a severe degradation of the impedance matching (i.e., will cause a severe impedance mis-match) between the input of the receiver and the traces on the PCB (Printed Circuit Board) due to the excessive capacitance loading. This results in even more undesirable and deleterious effects due to the large amount of reflections, and this significantly degrades the integrity of the input data. Another potential issue and problem of this prior art two path embodiment 100 is when the signals that pass through the two different paths are ultimately combined together at the summer, it may generate addition jitter if the delay between the two path differs significantly. As can be seen, while this prior art two path embodiment 100 does provide at least one solution to having an adjustable gain and equalizer stage, it has significant limitations. More specifically, among other problems, this prior art two path embodiment 100 significantly power consumptive, it may introduce undesirable impedance matches, and it may require great care be taken to ensure the two paths have substantially similar delays.
Cleary, there still exists a need in the art for a solution for an adjustable combined amplifier/equalizer stage accommodate various data channels while not increasing the power and loading, and not introducing many of the undesirable and deleterious effects generated by the prior art two path embodiment 100 described above.
From the above discussions, it is highly desirable to have an adjustable combined amplifier/equalizer stage accommodate various data channels while not increasing the power and loading.